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1 LTC1873 dual 550khz synchronous 2-phase switching regulator controller with 5-bit vid the ltc ? 1873 is a dual switching regulator controller opti- mized for high efficiency with low input voltages. it includes two complete, on-chip, independent switching regulator con- trollers. each is designed to drive a pair of external n-channel mosfets in a voltage mode feedback, synchro- nous buck configuration. the LTC1873 includes digital out- put voltage adjustment on side 1 that conforms to the intel desktop vid specification. a constant-frequency, true pwm design minimizes external component size and cost and optimizes load transient performance. the synchronous buck architecture automatically shifts to discontinuous and then to burst mode tm operation as the output load decreases, ensur- ing maximum efficiency over a wide range of load currents. the LTC1873 features an onboard reference trimmed to 1% and delivers better than 1.5% regulation at the converter outputs over all combinations of line, load and temperature. each channel can be enabled independently; with both chan- nels disabled, the LTC1873 shuts down and supply current drops below 100 m a. n two independent pwm controllers in one package n side 1 output is compliant with intel desktop vrm 8.4 specifications (includes 5-bit vid dac) n 1.3v to 3.5v output voltage with 50mv/100mv steps n two sides run out-of-phase to minimize c in n all n-channel external mosfet architecture n no external current sense resistors required n precison internal 0.8v 1% reference n 550khz switching frequency minimizes external component size n very fast transient response n up to 25a output current per channel n low shutdown current: < 100 m a n small 28-pin ssop package , ltc and lt are registered trademarks of linear technology corporation. burst mode is a trademark of linear technology corporation. n microprocessor core and i/o supplies n multiple logic supply generator n high efficiency power conversion n chipset power supply low cost desktop cpu supply with rdram keepalive + fb2 comp2 run/ss2 fb1 comp1 fcb vid4:0 boost2 tg2 sw2 bg2 i max2 v cc pv cc sgnd pgnd LTC1873 4.75k 0.1% 0.1 f 39pf 56pf 220pf 330pf 56k qss2 qss1 c in = sanyo 10mv1200gx (6 in parallel) c out1 = sanyo 6mv1500gx (8 in parallel) c out2 = sanyo 6mv1500gx (3 in parallel) l1: 1 h sumida cep125-1r0mc-h l2: 2.2 h coiltronics up2b-2r2 qss1, qss2: motorola mmbt3904lt1 qt1a, qt1b, qb1a, qb1b: fairchild fds6670a qt2, qb2: 1/2 siliconix si4966 4.5v to 5.5v stby/on 5-bit vid 1k 68k 1k 10k 0.1% 47k qt2 mbr0530t 1 f qb2 qt1a qt1b mbr0530t 1 f c out1 1873 ta01 + c out2 + 10 f + c in 1 f 16.9k 0.1% 16.2k 0.1% v rdram 2.5v/7a 2.45v/100ma standby v core 1.3v to 3.5v 20a 10 l1 qb1a qb1b 33k fault boost1 tg1 sw1 bg1 i max1 l2 in out gnd lt1761 adj run/ss1 sense descriptio u features applicatio s u typical applicatio u
2 LTC1873 (note 1) supply voltage v cc ........................................................................................... 7v boost n ............................................................... 15v boost n C sw n .................................................... 7v input voltage sw n .......................................................... C 1v to 8v vid n ....................................................... C 0.3v to 7v all other inputs ......................... C 0.3v to v cc + 0.3v peak output current < 10 m s tg n , bg n ............................................................... 5a operating temperature range (note 2) ............................................. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 55 c/ w LTC1873eg consult factory for industrial and military grade parts. symbol parameter conditions min typ max units main control loop v cc v cc supply voltage l 37v pv cc pv cc supply voltage (note 3) l 37v bv cc boost pin voltage v boost C v sw (note 3) l 2.7 7 v i cc v cc supply current test circuit 1 l 2.2 8 ma run/ss1 = run/ss2 = 0v (note 6) l 30 100 m a ipv cc pv cc supply current test circuit 1 (note 5) l 2.2 6 ma run/ss1 = run/ss2 = 0v (note 6) l 6 100 m a i boost boost pin current test circuit 1 (note 5) l 1.3 3 ma run/ss1 = run/ss2 = 0v l 0.1 10 m a v fb feedback voltage test circuit 1 l 0.790 0.800 0.810 v d v fb feedback voltage line regulation v cc = 3v to 7v l 0.005 0.05 %/v i fb feedback current fb2 only (note 7) l 0.001 1 m a v fcb fcb threshold l 0.75 0.8 0.85 v d v fcb fcb feedback hysteresis 20 mv i fcb fcb pin current l 0.001 1 m a v run run/ss pin run threshold l 0.45 0.55 0.65 v i ss soft start source current run/ss n = 0v C 1.5 C 3.5 C 5.5 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v unless otherwise specified. (note 4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pv cc boost1 bg1 tg1 sw1 i max1 fcb run/ss1 comp1 sgnd fb1 sense vid0 vid1 i max2 boost2 bg2 tg2 sw2 pgnd fault run/ss2 comp2 fb2 v cc vid4 vid3 vid2 absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 LTC1873 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LTC1873 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: pv cc and bv cc (v boost C v sw ) must be greater than v gs(on) of the external mosfets used to ensure proper operation. note 4: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v unless otherwise specified. (note 4) note 5: supply current in normal operation is dominated by the current needed to charge and discharge the external mosfet gates. this current will vary with supply voltage and the external mosfets used. note 6: supply current in shutdown is dominated by external mosfet leakage and may be significantly higher than the quiescent current drawn by the LTC1873, especially at elevated temperature. note 7: feedback current at fb1 will be higher due to internal vid resistors. note 8: each built-in pull-up resistor attached to the vid inputs also has a series diode connected to v cc to allow input voltages higher than the v cc supply without damage or clamping. (see block diagram.) note 9: rise and fall times are measured at 20% to 80% levels. delay and nonoverlap times are measured using 50% levels. electrical characteristics symbol parameter conditions min typ max units switching characteristics v osc oscillator amplitude 1v p-p f osc oscillator frequency test circuit 1 l 475 550 750 khz f osc2 controller 2 oscillator phase relative to controller 1 180 deg dc min1 minimum duty cycle v fb < v max l 710 % dc min2 minimum duty cycle v fb > v max l 0% dc max maximum duty cycle l 87 90 93 % t nov driver nonoverlap test circuit 1 (note 9) l 40 100 ns t r , t f driver rise/fall time test circuit 1 (note 9) l 12 80 ns feedback amplifier a vfb fb dc gain l 74 85 db gbw fb gain bandwidth 25 mhz i err fb sink/source current comp n output l 3 10 ma v min min comparator threshold l 760 785 mv v max max comparator threshold l 815 840 mv current limit loop a vilim i lim gain 40 db i imax i max source current i max = 0v l C7 C10 C14 m a status outputs v fault fault trip point v fb relative to regulated v out l +10 +15 +20 % v olf fault output low voltage i fault = 1ma l 0.03 0.1 v i fault fault output current v fault = 0v C 10 m a t fault fault delay time v fb > v fault to fault (note 9) 25 m s vid inputs r1 resistance between sense and fb1 side 1 only 20 k w v out error % output voltage accuracy programmed from 1.3v to 3.5v l C 1.5 1.5 % r pullup vid input pull-up resistance v diode = 0.6v (note 8) 40 k w vid t vid input voltage threshold v il (2.7v v cc 5.5v) 0.4 v v ih (2.7v v cc 5.5v) 1.6 v i vid-leak vid input leakage current v cc < vid < 7v (note 8) 0.01 1 m a v pullup vid pull-up voltage v cc = 3.3v 2.8 v v cc = 5v 4.5 v
4 LTC1873 10 m s/div typical perfor a ce characteristics uw efficiency vs load current temperature ( c) ?0 supply current (ma) 2.4 pv cc v cc 25 1873 g04 1.8 1.4 ?5 0 50 1.2 1.0 2.6 2.2 2.0 1.6 75 100 125 boost1, boost2 test circuit 1 c l = 0pf transient response temperature ( c) ?0 2.5 frequency drift (%) 2.0 1.0 0.5 0 2.5 1.0 0 50 75 1873 g05 1.5 1.5 2.0 0.5 ?5 25 100 125 v cc = 5v temperature ( c) ?0 0.4 r on ( ) 0.5 0.7 0.8 0.9 1.4 1.1 0 50 75 1873 g06 0.6 1.2 1.3 1.0 ?5 25 100 125 v pvcc = 5v v boost ?v sw = 5v mosfet driver supply current vs gate capacitance supply current vs temperature frequency drift vs temperature driver r on vs temperature run/ss source current vs temperature temperature ( c) ?0 source current ( a) 4.0 4.5 5.0 25 75 1873 g07 3.5 3.0 ?5 0 50 100 125 2.5 2.0 v cc = 5v nonoverlap time vs temperature driver rise/fall vs temperature load current (a) 0 70 efficiency (%) 80 90 100 510 1873 g01 15 v in = 5v v out = 3.3v v out = 2.5v v out = 1.6v v in = 5v v out = 1.8v i load = 0a-10a-0a 2.2% max deviation 1873 g02 gate capacitance (pf) 0 25 30 35 6000 8000 1873 g03 20 15 2000 4000 10000 10 5 0 driver supply current (ma) test circuit 1 one driver loaded multiply by # of active drivers to obtain total driver supply current temperature ( c) ?0 40 50 70 25 75 1873 g08 30 20 ?5 0 50 100 125 10 0 60 nonoverlap time (ns) test circuit 1 c l = 2000pf bg falling edge tg rising edge tg falling edge bg rising edge temperature ( c) 50 ?5 12 rise/fall time (ns) 12 15 0 50 75 1873 g09 11 14 13 25 100 125 test circuit 1 c l = 2000pf 20mv/ div
5 LTC1873 fcb (pin 7): force continuous bar. the fcb pin forces both converters to maintain continuous synchronous operation regardless of load when the voltage at fcb drops below 0.8v. fcb is normally tied to v cc . to force continuous operation, tie fcb to sgnd. fcb can also be connected to a feedback resistor divider from a secondary winding on one converters inductor to generate a third regulated output voltage. do not leave fcb floating. run/ss1 (pin 8): controller 1 run/soft-start. pulling run/ss1 to sgnd will disable controller 1 and turn off both of its external mosfet switches. pulling both run/ss pins down will shut down the entire LTC1873, dropping the quiescent supply current below 50 m a. a capacitor from run/ss1 to sgnd will control the turn-on time and rate of rise of the controller 1 output voltage at power-up. an internal 3.5 m a current source pull-up at run/ss1 pin sets the turn-on time at approximately 50ms/ m f. comp1 (pin 9): controller 1 loop compensation. the comp1 pin is connected directly to the output of the first controllers error amplifier and the input to the pwm comparator. an rc network is used at the comp1 pin to compensate the feedback loop for optimum transient response. sgnd (pin 10): signal ground. all internal low power circuitry returns to the sgnd pin. connect to a low impedance ground, separated from the pgnd node. all feedback, compensation and soft-start connections should return to sgnd. sgnd and pgnd should connect only at a single point, near the pgnd pin and the negative plate of the c in bypass capacitor. fb1 (pin 11): controller 1 feedback input. the loop compensation network for controller 1 should be con- nected to fb1. fb1 is connected internally to the vid resistor network to set the output voltage at side 1. sense (pin 12): output sense. connect to v out1 . vid0 to vid4 (pins 13 to 17): vid programming inputs. these are logic inputs that set the output voltage at side 1 to a preprogrammed value (see table 1). vid4 is the msb, vid0 is the lsb. the codes selected by the vid n inputs correspond to the intel desktop vid specification. each pv cc (pin 1): driver power supply input. pv cc provides power to the two bg n output drivers. pv cc must be connected to a voltage high enough to fully turn on the external mosfets qb1 and qb2. pv cc should generally be connected directly to v in . pv cc requires at least a 1 m f bypass capacitor directly to pgnd. boost1 (pin 2): controller 1 top gate driver supply. the boost1 pin supplies power to the floating tg1 driver. boost1 should be bypassed to sw1 with a 1 m f capacitor. an additional schottky diode from v in to boost1 pin will create a complete floating charge-pumped supply at boost1. no other external supplies are required. bg1 (pin 3): controller 1 bottom gate drive. the bg1 pin drives the gate of the bottom n-channel synchronous switch mosfet, qb1. bg1 is designed to drive up to 10,000pf of gate capacitance directly. if run/ss1 goes low, bg1 will go low, turning off qb1. if fault mode is tripped, bg1 will go high and stay high, keeping qb1 on until the power is cycled. tg1 (pin 4): controller 1 top gate drive. the tg1 pin drives the gate of the top n-channel mosfet, qt1. the tg1 driver draws power from the boost1 pin and returns to the sw1 pin, providing true floating drive to qt1. tg1 is designed to drive up to 10,000pf of gate capacitance directly. in shutdown or fault modes, tg1 will go low. sw1 (pin 5): controller 1 switching node. sw1 should be connected to the switching node of converter 1. the tg1 driver ground returns to sw1, providing floating gate drive to the top n-channel mosfet switch, qt1. the voltage at sw1 is compared to i max1 by the current limit comparator while the bottom mosfet, qb1, is on. i max1 (pin 6): controller 1 current limit set. the i max1 pin sets the current limit comparator threshold for controller 1. if the voltage drop across the bottom mosfet, qb1, exceeds the magnitude of the voltage at i max1 , controller 1 will go into current limit. the i max1 pin has an internal 10 m a current source pull-up, allowing the current threshold to be set with a single external resistor to pgnd. this current setting resistor should be kelvin connected to the source of qb1. see the current limit programming section for more information on choosing r imax . uu u pi fu ctio s
6 LTC1873 vid n pin includes an on-chip 40k w pull-up resistor in series with a diode (see block diagram). v cc (pin 18): power supply input. all internal circuits except the output drivers are powered from this pin. v cc should be connected to a low noise power supply voltage between 3v and 7v and should be bypassed to sgnd with at least a 1 m f capacitor in close proximity to the LTC1873. fb2 (pin 19): controller 2 feedback input. fb2 should be connected through a resistor divider network to v out2 to set the ouput voltage. the loop compensation network for controller 2 also connects to fb2. comp2 (pin 20): controller 2 loop compensation. see comp1. run/ss2 (pin 21): controller 2 run/soft-start. see run/ ss1. fault (pin 22): output overvoltage fault (latched). the fault pin is an open-drain output with an internal 10 m a pull-up. if either regulated output voltage rises more than 15% above its programmed value for more than 25 m s, the fault output will go high and the entire LTC1873 will be disabled. when fault is high, both bg pins will go high, turning on the bottom mosfet switches and pulling down the high output voltage. the LTC1873 will remain latched in this state until the power is cycled. when fault mode is active, the fault pin will be pulled up with an internal 10 m a current source. tying fault directly to sgnd will disable latched fault mode and will allow the LTC1873 to resume normal operation when the overvoltage fault is removed. pgnd (pin 23): power ground. the bg n drivers return to this pin. connect pgnd to a high current ground node in close proximity to the sources of external mosfets, qb1 and qb2, and the v in and v out bypass capacitors. sw2 (pin 24): controller 2 switching node. see sw1. tg2 (pin 25): controller 2 top gate drive. see tg1. bg2 (pin 26): controller 2 bottom gate drive. see bg1. boost2 (pin 27): controller 2 top gate driver supply. see boost1. i max2 (pin 28): controller 2 current limit set. see i max1 . v cc 5v 2k nc nc nc 2000pf 2000pf 2000pf 2000pf boost1 tg1 bg1 sw1 i max1 fcb vid0:4 run/ss1 comp1 fb1 sense LTC1873 boost2 tg2 bg2 sw2 i max2 fault run/ss2 comp2 fb2 0.1 f 100 f v fb1 v fb2 v fault i boost1 i cc i pvcc i boost2 f osc measured 1873 tc pv cc gnd pgnd + 2k test circuit 1 uu u pi fu ctio s test circuit
7 LTC1873 overview the LTC1873 is a dual, step-down (buck), voltage mode feedback switching regulator controller. it is designed to be used in a synchronous switching architecture with two external n-channel mosfets per channel. it is intended to operate from a low voltage input supply (7v maximum) and provide a high power, high efficiency, precisely regu- lated output voltage. several features make it particularly suited for microprocessor supply regulation. output regu- lation is extremely tight, with dc line and load regulation and initial accuracy better than 1.5%, and total regulation including transient response inside of 3.5% with a prop- burst logic soft start 90% duty cycle run/ss1,2 comp1,2 10 a 3.5 a 500mv 800mv 760mv 840mv i max1,2 drive logic osc 550khz + i lim fb min max 920mv flt 0v dis fcb fb1,2 1873 bd boost1,2 tg1,2 from other controller shutdown to this controller shutdown to entire chip fault pv cc 25 s delay from other controller v cc sw1,2 bg1,2 pgnd sgnd 10 a 40k vid0 v cc 40k vid1 v cc 40k vid2 v cc 40k vid3 v cc 40k vid4 v cc r11 20k r b1 sense to fb1 switch control logic erly designed circuit. the 550khz switching frequency allows the use of physically small, low value external components without compromising performance. an onboard dac sets the output voltage at channel 1, consis- tent with the intel desktop vid specification (table 1). the LTC1873s internal feedback amplifier is a 25mhz gain-bandwidth op amp, allowing the use of complex multipole/zero compensation networks. this allows the feedback loop to maintain acceptable phase margin at higher frequencies than traditional switching regulator controllers allow, improving stability and maximizing tran- sient response. the 800mv internal reference at channel 2 block diagra w applicatio s i for atio wu uu
8 LTC1873 allows regulated output voltages as low as 800mv without external level shifting amplifiers. the LTC1873s synchronous switching logic transitions automatically into burst mode operation, maximizing effi- ciency with light loads. an onboard overvoltage (ov) fault flag indicates when an ov fault has occurred. the ov flag can be set to latch the device off when an ov fault has occurred, or to automatically resume operation when the fault is removed. 2-phase operation the LTC1873 dual switching regulator controller offers considerable benefits using 2-phase operation. circuit benefits include lower input filtering requirements, reduced electromagnetic interference (emi) and increased efficiency associated with 2-phase operation. why the need for 2-phase operation? until recently, con- stant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). this means that both topside mosfets turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and input power supply. with 2-phase operation, the two channels of the LTC1873 are operated 180 degrees out of phase. this effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in total rms input current, which in turn allows less expensive input capaci- tors to be used, reduces shielding requirements for emi and improves real world operating efficiency. figure 7 shows example waveforms for a single switching regulator channel versus a 2-phase LTC1873 system with both sides switching. a single-phase dual regulator with both sides operating would exhibit double the single side numbers. in this example, 2-phase operation reduced the rms input current from 9.3a rms (2 4.66a rms ) to 4.8a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms 2 , meaning that the actual power wasted is reduced by a table 1. vid inputs and corresponding output voltage for channel 1 code vid4 vid3 vid2 vid1 vid0 v out1 00000 gnd gnd gnd gnd gnd 2.05v 00001 gnd gnd gnd gnd float 2.00v 00010 gnd gnd gnd float gnd 1.95v 00011 gnd gnd gnd float float 1.90v 00100 gnd gnd float gnd gnd 1.85v 00101 gnd gnd float gnd float 1.80v 00110 gnd gnd float float gnd 1.75v 00111 gnd gnd float float float 1.70v 01000 gnd float gnd gnd gnd 1.65v 01001 gnd float gnd gnd float 1.60v 01010 gnd float gnd float gnd 1.55v 01011 gnd float gnd float float 1.50v 01100 gnd float float gnd gnd 1.45v 01101 gnd float float gnd float 1.40v 01110 gnd float float float gnd 1.35v 01111 gnd float float float float 1.30v code vid4 vid3 vid2 vid1 vid0 v out1 10000 float gnd gnd gnd gnd 3.50v 10001 float gnd gnd gnd float 3.40v 10010 float gnd gnd float gnd 3.30v 10011 float gnd gnd float float 3.20v 10100 float gnd float gnd gnd 3.10v 10101 float gnd float gnd float 3.00v 10110 float gnd float float gnd 2.90v 10111 float gnd float float float 2.80v 11000 float float gnd gnd gnd 2.70v 11001 float float gnd gnd float 2.60v 11010 float float gnd float gnd 2.50v 11011 float float gnd float float 2.40v 11100 float float float gnd gnd 2.30v 11101 float float float gnd float 2.20v 11110 float float float float gnd 2.10v 11111* float float float float float 2.00v * 11111 is defined by intel to signify no cpu. the LTC1873 will generate the output voltage shown when this codes is selected. applicatio s i for atio wu uu
9 LTC1873 factor of 3.75. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. small footprint the LTC1873 operates at a 550khz switching frequency, allowing it to use low value inductors without generating excessive ripple currents. because the inductor stores less energy per cycle, the physical size of the inductor can be reduced without risking core saturation, saving pcb board space. the high operating frequency also means less energy is stored in the output capacitors between cycles, minimizing their required value and size. the remaining components, including the ssop-28 LTC1873, are tiny, allowing an entire dual-output LTC1873 circuit to be constructed in 1.5in 2 of pcb space. further, this space is generally located right next to the microprocessor or in some similarly congested area, where pcb real estate is at a premium. fast transient response the LTC1873 uses a fast 25mhz gbw op amp as an error amplifier. this allows the compensation network to be designed with several poles and zeros in a more flexible configuration than with a typical g m feedback amplifier. the high bandwidth of the amplifier, coupled with the high switching frequency and the low values of the external inductor and output capacitor, allow very high loop cross- over frequencies. the low inductor value is the other half of the equationwith a typical value on the order of 1 m h, the inductor allows very fast di/dt slew rates. the result is superior transient response compared with conventional solutions. high efficiency the LTC1873 uses a synchronous step-down (buck) architecture, with two external n-channel mosfets per output. a floating topside driver and a simple external charge pump provide full gate drive to the upper mosfet. the voltage mode feedback loop and mosfet v ds current limit sensing remove the need for an external current sense resistor, eliminating an external component and a source of power loss in the high current path. properly designed circuits using low gate charge mosfets are capable of efficiencies exceeding 90% over a wide range of output voltages. vid programming the LTC1873 includes an onboard feedback network that programs the output voltage at side 1 in accordance with the intel desktop vid specification (table 1). the network includes a 20k resistor (r1) connected from sense to fb1, and a variable value resistor (r b ) from fb1 to sgnd, with the value set by the digital code present at the vid0:4 pins. sense should be connected to v out1 to allow the network to monitor the output voltage. no additional feedback components are required to set the output volt- age at controller 1, although loop compensation compo- nents are still required. each vid n pin includes an internal 40k pull-up resistor, allowing it to float high if left uncon- nected. the pull-up resistors are connected to v cc through diodes (see block diagram), allowing the vid n pins to be pulled above v cc without damage. note that code 11111, defined by intel to indicate no cpu present, does generate an output voltage at v out1 (2.00v). note also that controller 2 on the LTC1873 is not con- nected to the vid circuitry, and works independently from controller 1. architecture details the LTC1873 dual switching regulator controller includes two independent regulator channels. the two sides of the chip and their corresponding external components act independently of each other with the exception of the common input bypass capacitor, the vid circuitry at side 1, and the fcb and fault pins, which affect both chan- nels. in the following discussions, when a pin is referred to without mentioning which side is involved, that discus- sion applies equally to both sides. applicatio s i for atio wu uu
10 LTC1873 switching architecture each half of the LTC1873 is designed to operate as a synchronous buck converter (figure 1). each channel includes two high power mosfet gate drivers to control external n-channel mosfets qt and qb. these drivers have 0.5 w output impedances and can carry well over an amp of continuous current with peak currents up to 5a to slew large mosfet gates quickly. the external mosfets are connected with the drain of qt attached to the input supply and the source of qt at the switching node sw. qb is the synchronous rectifier with its drain at sw and its source at pgnd. sw is connected to one end of the inductor, with the other end connected to v out . the output capacitor is connected from v out to pgnd. when a switching cycle begins, qb is turned off and qt is turned on. sw rises almost immediately to v in and the inductor current begins to increase. when the pwm pulse finishes, qt turns off and one nonoverlap interval later, qb turns on. now sw drops to pgnd and the inductor current decreases. the cycle repeats with the next tick of the master clock. the percentage of time spent in each mode is controlled by the duty cycle of the pwm signal, which in turn is controlled by the feedback amplifier. the master clock runs at a 550khz rate and turns qt once every 1.8 m s. in a typical application with a 5v input and a 1.5v output, the duty cycle will be set at 1.5/5 100% or 30% by the feedback loop. this will give roughly a 540ns on-time for qt and a 1.26 m s on-time for qb. this constant frequency operation brings with it a couple of benefits. inductor and capacitor values can be chosen with a precise operating frequency in mind and the feed- back loop components can be similarly tightly specified. noise generated by the circuit will always be in a known frequency band with the 550khz frequency designed to leave the 455khz if band free of interference. subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC1873. during the time that qt is on, its source (the sw pin) is at v in . v in is also the power supply for the LTC1873. how- ever, qt requires v in + v gs(on) at its gate to achieve minimum r on . this presents a problem for the LTC1873 it needs to generate a gate drive signal at tg higher than its highest supply voltage. to accomplish this, the tg driver runs from floating supplies, with its negative supply attached to sw and its power supply at boost. this allows it to slew up and down with the source of qt. in combination with a simple external charge pump (figure 2), this allows the LTC1873 to completely enhance the gate of qt without requiring an additional, higher supply voltage. the two channels of the LTC1873 run from a common clock, with the phasing chosen to be 180 from side 1 to side 2. this has the effect of doubling the frequency of the switching pulses seen by the input bypass capacitor, significantly lowering the rms current seen by the capaci- tor and reducing the value required (see the 2-phase section). feedback amplifier each side of the LTC1873 senses the output voltage at v out with an internal feedback op amp (see block dia- gram). this is a real op amp with a low impedance output, 85db open-loop gain and 25mhz gain-bandwidth product. the positive input is connected internally to an 800mv reference, while the negative input is connected to the fb figure 1. synchronous buck architecture + tg 1/2 LTC1873 bg sw pgnd c out 1873 f01 + c in qt qb v out v in l ext figure 2. floating tg driver supply + tg boost sw bg pgnd pv cc d cp c in + c out 1873 f02 v out l ext v in qt qb c cp 1 f LTC1873 applicatio s i for atio wu uu
11 LTC1873 pin. the output is connected to comp, which is in turn connected to the soft-start circuitry and from there to the pwm generator. unlike many regulators that use a resistor divider con- nected to a high impedance feedback input, the LTC1873 is designed to use an inverting summing amplifier topol- ogy with the fb pin configured as a virtual ground. this allows flexibility in choosing pole and zero locations not available with simple g m configurations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and significantly improves loop phase margin (see figure 3). the feedback loop/compensation section contains a detailed explana- tion of type 3 feedback loops. note that side 1 of the LTC1873 includes r1 and r b internally as part of the vid dac circuitry. min/max comparators two additional feedback loops keep an eye on the primary feedback amplifier and step in if the feedback node moves 5% from its nominal 800mv value. the max comparator (see block diagram) activates whenever fb rises more than 5% above 800mv. it immediately turns the top mosfet (qt) off and the bottom mosfet (qb) on and keeps them that way until fb falls back within 5% of its nominal value. this pulls the output down as fast as possible, preventing damage to the (often expensive) load. if fb rises because the output is shorted to a higher supply, qb will stay on until the short goes away, the higher supply current limits or qb dies trying to save the load. this behavior provides maximum protection against overvoltage faults at the output, while allowing the circuit figure 3. type 3 feedback loop (side 2 shown) 0.8v v out r b 1873 f03 comp + fb fb c2 c3 c1 r2 r1 r3 to resume normal operation when the fault is removed. the overvoltage protection circuit can optionally be set to latch the output off permanently (see the overvoltage fault section). the min comparator (see block diagram) trips whenever fb is more than 5% below 800mv and immediately forces the switch duty cycle to 90% to bring the output voltage back into range. it releases when fb is within the 5% window. min is disabled when the soft-start or current limit circuits are activethe only two times that the output should legitimately be below its regulated value. notice that the fb pin is the virtual ground node of the feedback amplifier. a typical compensation network does not include local dc feedback around the amplifier, so that the dc level at fb will be an accurate replica of the output voltage, divided down by r1 and r b (figure 3). however, the compensation capacitors will tend to attenuate ac signals at fb, especially with low bandwidth type 1 feed- back loops. this creates a situation where the min and max comparators do not respond immediately to shifts in the output voltage, since they monitor the output at fb. maximizing feedback loop bandwidth will minimize these delays and allow min and max to operate properly. see the feedback loop/compensation section. shutdown/soft-start each half of the LTC1873 has a run/ss pin. the run/ss pins perform two functions: when pulled to ground, each shuts down its half of the LTC1873, and each acts as a conventional soft-start pin, enforcing a maximum duty cycle limit proportional to the voltage at run/ss. an internal 3.5 m a current source pull-up is connected to each run/ss pin, allowing a soft-start ramp to be generated with a single external capacitor to ground. the 3.5 m a current sources are active even when the LTC1873 is shut down, ensuring the device will start when any external pull-down at run/ss is released. either side can be shut down without affecting the operation of the other side. if both sides are shut down at the same time, the LTC1873 goes into a micropower sleep mode, and quiescent cur- rent drops typically below 50 m a. entering sleep mode also resets the fault latch, if it was set. applicatio s i for atio wu uu
12 LTC1873 each run/ss pin shuts down its half of the LTC1873 when it falls below about 0.5v (figure 4). between 0.5v and about 1v, that half is active, but the maximum duty cycle is limited to 10%. the maximum duty cycle limit increases linearly between 1v and 2.5v, reaching its final value of 90% when run/ss is above 2.5v. somewhere before this point, the feedback amplifier will assume control of the loop and the output will come into regulation. when run/ ss rises to 0.5v below v cc , the min feedback comparator is enabled, and the LTC1873 is in full operation. current limit the LTC1873 includes an onboard current limit circuit that limits the maximum output current to a user-programmed level. it works by sensing the voltage drop across qb during the time that qb is on and comparing that voltage to a user-programmed voltage at i max . since qb looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. in a buck converter, the average current in the inductor is equal to the output current. this current also flows through qb during its on-time. thus, by watching the voltage across qb, the LTC1873 can monitor the output current. any time qb is on and the current flowing to the output is reasonably large, the sw node at the drain of qb will be somewhat negative with respect to pgnd. the LTC1873 senses this voltage and inverts it to allow it to compare the sensed voltage with a positive voltage at the i max pin. the i max pin includes a trimmed 10 m a pull-up, enabling the user to set the voltage at i max with a single resistor, r imax , to ground. the LTC1873 compares the two inputs and begins limiting the output current when the magnitude of the negative voltage at the sw pin is greater than the voltage at i max . the current limit detector is connected to an internal g m amplifier that pulls a current from the run/ss pin propor- tional to the difference in voltage magnitudes between the sw and i max pins. this current begins to discharge the soft-start capacitor at run/ss, reducing the duty cycle and controlling the output voltage until the current drops below the limit. the soft-start capacitor needs to move a fair amount before it has any effect on the duty cycle, adding a delay until the current limit takes effect (figure 4). this allows the LTC1873 to experience brief overload conditions without affecting the output voltage regulation. the delay also acts as a pole in the current limit loop to 2.5v 2.5v 1.0v 0v 5v 0v v out v run/ss 4.5v run/ss controls duty cycle min comparator enabled run/ss controls duty cycle start-up normal operation current limit 1873 f04 comp controls duty cycle LTC1873 enabled 0.5v figure 4. soft-start operation in start-up and current limit applicatio s i for atio wu uu
13 LTC1873 enhance loop stability. larger overloads cause the soft- start capacitor to pull down quickly, protecting the output components from damage. the current limit g m amplifier includes a clamp to prevent it from pulling run/ss below 0.5v and shutting off the device. power mosfet r ds(on) varies from mosfet to mosfet, limiting the accuracy obtainable from the LTC1873 current limit loop. additionally, ringing on the sw node due to parasitics can add to the apparent current, causing the loop to engage early. the LTC1873 current limit is designed primarily as a disaster prevention, no blow up circuit, and is not useful as a precision current regulator. it should typically be set around 50% above the maximum expected normal output current to prevent component tolerances from encroaching on the normal current range. see the current limit programming section for advice on choosing a valve for r imax . discontinuous/burst mode operation theory of operation the LTC1873 switching logic has three modes of opera- tion. under heavy loads, it operates as a fully synchro- nous, continuous conduction switching regulator. in this mode of operation (continuous mode), the current in the inductor flows in the positive direction (toward the output) during the entire switching cycle, constantly supplying current to the load. in this mode, the synchronous switch (qb) is on whenever qt is off, so the current always flows through a low impedance switch, minimizing voltage drop and power loss. this is the most efficient mode of opera- tion at heavy loads, where the resistive losses in the power devices are the dominant loss term. continuous mode works efficiently when the load current is greater than half of the ripple current in the inductor. in a buck converter like the LTC1873, the average current in the inductor (averaged over one switching cycle) is equal to the load current. the ripple current is the difference between the maximum and the minimum current during a switching cycle (see figure 5a). the ripple current depends on inductor value, clock frequency and output voltage, but is constant regardless of load as long as the LTC1873 remains in continuous mode. see the inductor selection section for a detailed description of ripple current. as the output load current decreases in continuous mode, the average current in the inductor will reach a point where it drops below half the ripple current. at this point, the current in the inductor will reverse during a portion of the switching cycle, or begin to flow from the output back to the input. this does not adversely affect regulation, but does cause additional losses as a portion of the inductor current flows back and forth through the resistive power switches, giving away a little more power each time and lowering the efficiency. there are some benefits to allow- ing this reverse current flow: the circuit will maintain regulation even if the load current drops below zero (the load supplies current to the LTC1873) and the output ripple voltage and frequency remain constant at all loads, easing filtering requirements. circuits that take advantage of this behavior can force the LTC1873 to operate in continuous mode at all loads by tying the fcb (force continuous bar) pin to ground. discontinuous mode to minimize the efficiency loss due to reverse current flow at light loads, the LTC1873 switches to a second mode of operation: discontinuous mode (figure 5b). in discontinu- ous mode, the LTC1873 detects when the inductor current approaches zero and turns off qb for the remainder of the switch cycle. during this time, the voltage at the sw pin will float about v out , the voltage across the inductor will be zero, and the inductor current remains zero until the next switching cycle begins and qt turns on again. this prevents current from flowing backwards in qb, eliminat- ing that power loss term. it also reduces the ripple current in the inductor as the output current approaches zero. the LTC1873 detects that the inductor current has reached zero by monitoring the voltage at the sw pin while qb is on. since qb acts like a resistor, sw should ideally be right at 0v when the inductor current reaches zero. in reality, the sw node will ring to some degree immediately after it is switched to ground by qb, causing some uncertainty as to the actual moment the average current in qb goes to zero. the LTC1873 minimizes this effect by ignoring the sw node for a fixed 50ns after qb turns on when the ringing applicatio s i for atio wu uu
14 LTC1873 is most severe, and by including a few millivolts offset in the comparator that monitors the sw node. despite these precautions, some combinations of inductor and layout parasitics can cause the LTC1873 to enter discontinuous mode erratically. in many cases, the time that qb turns off will correspond to a peak in the ringing waveform at the sw pin (figure 6). this erratic operation isnt pretty, but retains much of the efficiency benefit of discontinuous mode and maintains regulation at all times. figure 5a. continuous mode figure 5b. discontinuous mode burst mode operation discontinuous mode removes a loss term due to resistive drop in qb, but the LTC1873 is still switching qt and qb on and off once a cycle. each time an external mosfet is turned on, the internal driver must charge its gate to v cc . each time it is turned off, that charge is lost to ground. at the high switching frequencies that the LTC1873 operates at, the charge lost to the gates can add up to tens of milliamps from v cc . as the load current continues to drop, this quickly become the dominant power loss term, reduc- ing efficiency once again. once again, the LTC1873 switches to a new mode to minimize efficiency loss: burst mode operation. as the circuit goes deeper and deeper into discontinuous mode, the total time qt and qb are on reduces. however, the ratio of the time that qt is on to the time that qb is on must remain constant for the output to stay in regulation. an internal timer circuit forces qt to stay on for at least 10% of a normal switching cycle. when the load drops to the point that the output requires less than 10% on-time at qt, the output voltage will begin to rise. the LTC1873 senses this rise and shuts both qt and qb off completely, skip- ping several switching cycles until the output falls back into range. it then resumes switching in discontinuous mode with qt at 10% duty cycle and the burst sequence repeats. the total deviation from the regulated output is within the 1.5% regulation tolerance of the LTC1873. in burst mode operation, both resistive loss and switching loss are minimized while keeping the output in regulation. the ripple current will be set by the 10% qt on-time and the input supply voltage and is the lowest of all three operating modes. as the load current falls to zero in burst mode operation, the most significant loss term becomes the 3ma quiescent current drawn by each side of the LTC1873usually much less than the minimum load current in a typical low voltage logic system. burst mode operation maximizes efficiency at low load currents, but can cause low frequency ripple in the output voltage as the cycle-skipping circuitry switches on and off. time i ripple i average inductor current 1873 f05a time i ripple i average inductor current 1873 f05b figure 6. ringing at sw causes discontinuous comparator to trip early time 50ns blank time 0v 0v 5v discontinuous comparator turns off bg v sw v bg 1873 f06 time applicatio s i for atio wu uu
15 LTC1873 fcb pin in some circumstances, it is desirable to control or disable discontinuous and burst mode operations. the fcb (force continuous bar) pin allows the user to do this. when the fcb pin is high, the LTC1873 is allowed to enter discon- tinuous and burst mode operations at either side as required. if fcb is taken low, discontinuous and burst mode operations are disabled and both sides of the LTC1873 run in continuous mode regardless of load. this does not affect output regulation but does reduce effi- ciency at low output currents. the fcb pin threshold is specified at 0.8v 50mv, and includes 20mv of hyster- esis, allowing it to be used as a precision small-signal comparator. paralleling outputs synchronous regulators (like the LTC1873) are known for their bullheadedness when their outputs are paralleled with other regulators. in particular, a synchronous regu- lator paralleled with another regulator whose output is slightly higher (perhaps just by millivolts) will happily sink amps of current attempting to pull its own output back down to what it thinks is the right value. the LTC1873 discontinuous mode allows it to be paral- leled with another regulator without fighting. a typical system might use the LTC1873 as a primary regulator and a small ldo as a backup regulator to keep sram alive when the main power is off. when the LTC1873 is shut down (by pulling run/ss to ground), both qt and qb turn off and the output goes into a high impedance state, allowing the smaller regulator to support the output volt- age. however, if the LTC1873 is powered back up in continuous mode, it will begin a soft-start cycle with a low duty cycle, pulling the output down and corrupting the data stored in sram. the solution is to tie fcb high, allowing the device to start in discontinuous mode. any reverse current flow in qb will trip the discontinuous mode circuitry, preventing the LTC1873 from pulling down the output. overvoltage fault the LTC1873 includes a single overvoltage fault flag for both channels: fault. fault is an open-drain output with an internal 10 m a pull-up. if either fb pin rises more than 15% above the nominal 800mv value for more than 25 m s, the overvoltage comparator will trip, setting an internal latch. this latch releases the pull-down at fault, allowing the 10 m a pull-up to take it high. when fault goes high, the LTC1873 stops all switching, turns both qb (bottom synchronous) mosfets on continuously and remains in this state until both run/ss pins are pulled low simultaneously, the power supply is recycled, or the fault pin is pulled low externally. this behavior is intended to protect a potentially expensive load from overvoltage damage at all costs. under some conditions, this behavior can cause the output voltage to undershoot below ground. if latched fault mode is used, a schottky diode should be added with its cathode at the output and its anode at ground to clamp the negative voltage to a safe level and prevent possible damage to the load and the output capacitors. note that in overvoltage conditions, the max comparator will kick in at just +5%, turning qb on continuously long before the output reaches +15%. under most fault condi- tions, this is adequate to bring the output back down without firing the fault latch. additionally, if max success- fully keeps the output below +15%, the LTC1873 will resume normal regulation as soon as the output overvolt- age fault is resolved. in some circuits, the ov latch can be a liability. consider a circuit where the output voltage at one channel may be changed on the fly by changing the vid code or switching in different feedback resistors. a downward adjustment of greater than 15% will fire the fault latch, disabling both sides of the LTC1873 until the power is recycled. in circuits such as this, the fault latch can be disabled by grounding the fault pin. the internal latch will still be set the first time the output exceeds +15%, but the 10 m a current source pull-up will not be able to pull fault high, and the LTC1873 will ignore the latch and continue applicatio s i for atio wu uu
16 LTC1873 normal opera tion. the max comparator will act as usual, turning on qb until output is within range and then allowing the loop to resume normal operation. fault can also be pulled down with external open-collector logic to restart a fault-latched LTC1873 as an alternative to recy- cling the power. note that this will not reset the internal latch; if the external pull-down is released, the LTC1873 will reenter fault mode. to reset the latch, pull both run/ ss pins low simultaneously or cycle the power. vid considerations some applications change the vid codes at channel 1 on the fly. this is possible with the LTC1873, but care must be taken to avoid tripping the overvoltage fault circuit. stepping the voltage upwards abruptly is safe, but step- ping down quickly by more than 15% can leave the system in a state where the output voltage is still at the old higher level, but the feedback node is set to expect a new, substantially lower voltage. if this condition persists for more than 25 m s, the overvoltage fault circuitry will activate and latch off the LTC1873. the simplest solution is to disable the fault circuit by grounding the fault pin. systems that must keep the fault circuit active should ensure that the output voltage is never programmed to step down by more than 15% in any single step. a safe strategy is to step the output down by 10% or less at a time and wait for the output to settle to the new value before taking subsequent steps. regardless of the state of the fault pin, the load is always protected against overvoltage faults by the +5% max comparator. external component selection power mosfets getting peak efficiency out of the LTC1873 depends strongly on the external mosfets used. the LTC1873 requires at least two external mosfets per sidemore if one or more of the mosfets are paralleled to lower on-resis- tance. to work efficiently, these mosfets must exhibit low r ds(on) at 5v v gs (3.3v v gs if the pv cc input supply is 3.3v) to minimize resistive power loss while they are conducting current. they must also have low gate charge to minimize transition losses during switching. on the other hand, voltage breakdown requirements in a typical LTC1873 circuit are pretty tame: the 7v maximum input voltage limits the v ds and v gs the mosfets can see to safe levels for most devices. low r ds(on) r ds(on) calculations are pretty straightforward. r ds(on) is the resistance from the drain to the source of the mosfet when the gate is fully on. many mosfets have r ds(on) specified at 4.5v gate drivethis is the right number to use in LTC1873 circuits running from a 5v supply. as current flows through this resistance while the mosfet is on, it generates i 2 r watts of heat, where i is the current flowing (usually equal to the output current) and r is the mosfet r ds(on) . this heat is only generated when the mosfet is on. when it is off, the current is zero and the power lost is also zero (and the other mosfet is busy losing power). this lost power does two things: it subtracts from the power available at the output, costing efficiency, and it makes the mosfet hotterboth bad things. the effect is worst at maximum load when the current in the mosfets and thus the power lost are at a maximum. lowering r ds(on) improves heavy load efficiency at the expense of additional gate charge (usually) and more cost (usually). proper choice of mosfet r ds(on) becomes a trade-off between tolerable efficiency loss, power dissipation and cost. note that while the lost power has a significant effect on system efficiency, it only adds up to a watt or two in a typical LTC1873 circuit, allowing the use of small, surface mount mosfets without heat sinks. gate charge gate charge is the amount of charge (essentially, the number of electrons) that the LTC1873 needs to put into the gate of an external mosfet to turn it on. the easiest way to visualize gate charge is to think of it as a capacitance from the gate pin of the mosfet to sw (for qt) or to pgnd (for qb). this capacitance is composed of mosfet chan- nel charge, actual parasitic drain-source capacitance and miller-multiplied gate-drain capacitance, but can be approximated as a single capacitance from gate to source. regardless of where the charge is going, the fact remains applicatio s i for atio wu uu
17 LTC1873 that it all has to come out of v cc to turn the mosfet gate on, and when the mosfet is turned back off, that charge all ends up at ground. in the meanwhile, it travels through the LTC1873s gate drivers, heating them up. more power lost! in this case, the power is lost in little bite-sized chunks, one chunk per switch per cycle, with the size of the chunk set by the gate charge of the mosfet. every time the mosfet switches, another chunk is lost. clearly, the faster the clock runs, the more important gate charge becomes as a loss term. old-fashioned switchers that ran at 20khz could pretty much ignore gate charge as a loss term; in the 550khz LTC1873, gate charge loss can be a significant efficiency penalty. gate charge loss can be the dominant loss term at medium load currents, especially with large mosfets. gate charge loss is also the primary cause of power dissipation in the LTC1873 itself. tg charge pump theres another nuance of mosfet drive that the LTC1873 needs to get around. the LTC1873 is designed to use n-channel mosfets for both qt and qb, primarily because n-channel mosfets generally cost less and have lower r ds(on) than similar p-channel mosfets. turning qb on is no big deal since the source of qb is attached to pgnd; the LTC1873 just switches the bg pin between pgnd and v cc . driving qt is another matter. the source of qt is connected to sw which rises to v cc when qt is on. to keep qt on, the LTC1873 must get tg one mosfet v gs(on) above v cc . it does this by utilizing a floating driver with the negative lead of the driver attached to sw (the source of qt) and the v cc lead of the driver coming out separately at boost. an external 1 m f capacitor (c cp ) connected between sw and boost (figure 2) supplies power to boost when sw is high, and recharges itself through d cp when sw is low. this simple charge pump keeps the tg driver alive even as it swings well above v cc . the value of the bootstrap capacitor c cp needs to be at least 100 times that of the total input capacitance of the topside mosfet(s). for very large external mosfets (or multiple mosfets in parallel), c cp may need to be increased beyond the 1 m f value. input supply the bicmos process that allows the LTC1873 to include large mosfet drivers on-chip also limits the maximum input voltage to 7v. this limits the practical maximum input supply to a loosely regulated 5v or 6v rail. the LTC1873 will operate properly with input supplies down to about 3v, so a typical 3.3v supply can also be used if the external mosfets are chosen appropriately (see the power mosfets section). at the same time, the input supply needs to supply several amps of current without excessive voltage drop. the input supply must have regulation adequate to prevent sudden load changes from causing the LTC1873 input voltage to dip. in most typical applications where the LTC1873 is generating a secondary low voltage logic supply, all of these input conditions are met by the main system logic supply when fortified with an input bypass capacitor. input bypass capacitor a typical LTC1873 circuit running from a 5v logic supply might provide 1.6v at 10a at one of its outputs. 5v to 1.6v implies a duty cycle of 32%, which means qt is on 32% of each switching cycle. during qts on-time, the current drawn from the input equals the load current and during the rest of the cycle, the current drawn from the input is near zero. this 0a to 10a, 32% duty cycle pulse train adds up to 4.7a rms at the input. at 550khz, switching cycles last about 1.8 m smost system logic supplies have no hope of regulating output current with that kind of speed. a local input bypass capacitor is required to make up the difference and prevent the input supply from dropping drastically when qt kicks on. this capacitor is usually chosen for rms ripple current capability and esr as well as value. the input bypass capacitor in an LTC1873 circuit is common to both channels. consider our 10a example case with the other side of the LTC1873 disabled. the input bypass capacitor gets exercised in three ways: its esr must be low enough to keep the initial drop as qt turns on within reason (100mv or so); its rms current capability must be adequate to withstand the 4.7a rms ripple current at the input and the capacitance must be large enough to applicatio s i for atio wu uu
18 LTC1873 figure 7. current waveforms maintain the input voltage until the input supply can make up the difference. generally, a capacitor that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. in our example, we need 0.01 w esr to keep the input drop under 100mv with a 10a current step and 4.7a rms ripple current capacity to avoid overheating the capacitor. these requirements can be met with multiple low esr tantalum or electrolytic capacitors in parallel, or with a large mono- lithic ceramic capacitor. the two sides of the LTC1873 run off a single master clock and are wired 180 out of phase with each other to significantly reduce the total capacitance/esr needed at the input. assuming 100mv of ripple and 10a output current, we needed an esr of 0.01 w and 4.7a ripple current capability for one side. now, assume both sides are running simultaneously with identical loading. if the two sides switched in phase, all the loading conditions would double and wed need enough capacitance for 9.4a rms and 0.005 w esr. with the two sides out of phase, the input current is 4.8a rms barely larger than the single case (figure 7)! the peak current deltas are still only 10a, requiring the same 0.01 w esr rating. as long as the capacitor we chose for the single side application can support the slightly higher 4.8a rms current, we can add the second channel without changing the input ca- pacitor at all. as a general rule, an input bypass capacitor capable of supporting the larger output current channel 0 10a 32% 68% 0 10a 32% 18% 18% 18% 32% 3.2a 0 6.8a 32% 68% qt current, side 1 only (for 1-phase, 2 sides: multiply current by 2) current in c in , side 1 only i cin = 4.66a rms , (1-phase, 2 sides: i cin = 9.3a rms ) current in c in , both sides equal load i cin = 4.8a rms qt1 current qt2 current both sides equal load 2-phase operation 6.4a 0 3.6a 32% 18% 1873 f07 32% calculating rms current in c in a buck regulator like the LTC1873 draws pulses of current from the input capacitor during normal opera- tion. the input capacitor sees this as ac current, and dissipates power proportional to the rms value of the input current waveform. to properly specify the capaci- tor, we need to know the rms value of the input current. calculating the approximate rms value of a pulse train with a fixed duty cycle is straightforward, but the LTC1873 complicates matters by running two sides simultaneously and out of phase, creating a complex waveform at the input. to calculate the approximate rms value of the input current, we first need to calculate the average dc value with both sides of the LTC1873 operating at maximum load. over a single period, the system will spend some time with one top switch on and the other off, perhaps some time with both switches on, and perhaps some time with both switches off. during the time each top switch is on, the current will equal that sides full load output current. when both switches are on, the total current will be the sum of the two full load currents, and when both are off, the current is effectively zero. multiply each current value by the percentage of the period that the current condition lasts, and sum the resultsthis is the average dc current value. as an example, consider a circuit that takes a 5v input and generates 3.3v at 3a at side 1 and 1.6v at 10a at side 2. when a cycle starts, tg1 turns on and 3a flows time 0abcd 50% 16% 16% 18% i ave 0 input current (a) 5.2 3 10 13 1873 sb1 figure sb1. average current calculation applicatio s i for atio wu uu
19 LTC1873 from c in (time point a). 50% of the way through, tg2 turns on and the total current is 13a (time point b). shortly thereafter, tg1 turns off and the current drops to 10a (time point c). finally, tg2 turns off and the current spends a short time at 0 before tg1 turns on again (time point d). ia a aa a avg = () + () + () + () = 305 13016 10 016 0 018 518 . . . . . now we can calculate the rms current. using the same waveform we used to calculate the average dc current, subtract the average current from each of the dc values. square each current term and multiply the squares by the same period percentages we used to calculate the aver- age dc current. sum the results and take the square root. the result is the approximate rms current as seen by the input capacitor with both sides of the LTC1873 at full load. actual rms current will differ due to inductor ripple time 0abcd 50% 16% 16% 18% 5.2 ac input current (a) 0 2.2 4.8 7.8 1873 sb2 figure sb2. ac current calculation current and resistive losses, but this approximate value is adequate for input capacitor calculation purposes. i a rms rms = () + () + () + () = . . . . .. .. . 218 05 782 016 482 016 518 018 455 22 22 if the circuit is likely to spend time with one side operating and the other side shut down, the rms current will need to be calculated for each possible case (side 1 on, side 2 off; side 1 off, side 2 on; both sides on). the capacitor must be sized to withstand the largest rms current of the threesometimes this occurs with one side shut down! side only ia a a ia side only iaa a i ave rms rms ave rms 1 3 0 67 0 0 33 2 01 1 0 67 2 0 33 1 42 2 10 032 0 068 32 68 032 32 068 1 1 22 2 2 22 : . . . . . . : . . . .. .. = () + () = = () + () = = () + () = = () + () = 4 466 455 .. aa rms rms > consider the case where both sides are operating at the same load, with a 50% duty cycle at each side. the rms current with both sides running is near zero, while the rms current with one side active is 1/2 the total load current of that side. can sup port both channels running simultaneously (see the 2-phase operation section for more information). details on how to calculate the maximum rms input current can be found in application note 77. tantalum capacitors are a popular choice as input capaci- tors for LTC1873 applications, but they deserve a special caution here. generic tantalum capacitors have a destruc- tive failure mechanism when they are subjected to large rms currents (like those seen at the input of a LTC1873). at some random time after they are turned on, they can blow up for no apparent reason. the capacitor manufac- turers are aware of this and sell special surge tested tantalum capacitors specifically designed for use with switching regulators. when choosing a tantalum input capacitor, make sure that it is rated to carry the rms current that the LTC1873 will draw. if the data sheet doesnt give an rms current rating, chances are the capacitor isnt surge tested. dont use it! applicatio s i for atio wu uu
20 LTC1873 output bypass capacitor the output bypass capacitor has quite different require- ments from the input capacitor. the ripple current at the output of a buck regulator like the LTC1873 is much lower than at the input, due to the fact that the inductor current is constantly flowing at the output whenever the LTC1873 is operating in continuous mode. the primary concern at the output is capacitor esr. fast load current transitions at the output will appear as voltage across the esr of the output bypass capacitor until the feedback loop in the LTC1873 can change the inductor current to match the new load current value. this esr step at the output is often the single largest budget item in the load regulation calculation. as an example, our hypothetical 1.6v, 10a switcher with a 0.01 w esr output capacitor would expe- rience a 100mv step at the output with a 0 to 10a load stepa 6.3% output change! usually the solution is to parallel several capacitors at the output. for example, to keep the transient response inside of 3% with the previous design, wed need an output esr better than 0.0048 w . this can be met with three 0.014 w , 470 m f tantalum capacitors in parallel. inductor the inductor in a typical LTC1873 circuit is chosen prima- rily for value and saturation current. the inductor value sets the ripple current, which is commonly chosen at around 30% of the anticipated full load current. ripple current is set by: i tv l ripple on qb out = () () in our hypothetical 1.6v, 10a example, we'd set the ripple current to 30% of 10a or 3a, and the inductor value would be: l tv i sv a h with t v v khz s on qb out ripple on qb = () = m ()() =m =- ? ? ? ? =m () () .. . . /. 12 16 4 05 1 16 5 550 1 2 the inductor must not saturate at the expected peak current. in this case, if the current limit was set to 15a, the inductor should be rated to withstand 15a + 1/2 i ripple , or 16.5a without saturating. feedback loop/compensation 1 feedback loop types in a typical LTC1873 circuit, the feedback loop consists of the modulator, the external inductor and output capacitor, and the feedback amplifier and its compensation network. all of these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the internal pwm generator, the output mosfet drivers and the external mosfets themselves. from a feedback loop point of view, it looks like a linear voltage transfer function from comp to sw and has a gain roughly equal to the input voltage. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll-off at the output, with the attendant 180 phase shift. this roll-off is what filters the pwm waveform, resulting in the desired dc output voltage, but the phase shift complicates the loop compensation if the gain is still higher than unity at the pole frequency. eventually (usually well above the lc pole frequency), the reactance of the output capacitor will approach its esr, and the roll-off due to the capacitor will stop, leaving 6db/octave and 90 of phase shift (figure 8). figure 8. ideal transfer function of buck modulator gain (db) phase (deg) 1873 f08 a v 00 ?0 180 6db/oct phase gain ?2db/oct 1 the information in this section is based on the paper the k factor: a new mathematical tool for stability analysis and synthesis by h. dean venable, venable industries, inc. for complete paper, see reference reading #4 at www.linear-tech.com. applicatio s i for atio wu uu
21 LTC1873 so far, the ac response of the loop is pretty well out of the users control. the modulator is a fundamental piece of the LTC1873 design, and the external l and c are usually chosen based on the regulation and load current require- ments without considering the ac loop response. the feedback amplifier, on the other hand, gives us a handle with which to adjust the ac response. the goal is to have 180 phase shift at dc (so the loop regulates) and some- thing less than 360 phase shift at the point that the loop gain falls to 0db. the simplest strategy is to set up the feedback amplifier as an inverting integrator, with the 0db frequency lower than the lc pole (figure 9). this type 1 configuration is stable but transient response will be less than exceptional if the lc pole is at a low frequency. type 2 loops work well in systems where the esr zero in the lc roll-off happens close to the lc pole, limiting the total phase shift due to the lc. the additional phase compensation in the feedback amplifier allows the 0db point to be at or above the lc pole frequency, improving loop bandwidth substantially over a simple type 1 loop. it has limited ability to compensate for lc combinations where low capacitor esr keeps the phase shift near 180 for an extended frequency range. LTC1873 circuits using conventional switching grade electrolytic output capaci- tors can often get acceptable phase margin with type 2 compensation. type 3 loops (figure 11) use two poles and two zeros to obtain a 180 phase boost in the middle of the frequency band. a properly designed type 3 circuit can maintain acceptable loop stability even when low output capacitor esr causes the lc section to approach 180 phase shift well above the initial lc roll-off. as with a type 2 circuit, the out in r1 c1 r b 1873 f09a v ref + gain (db) phase (deg) 1873 f09b 00 ?0 180 270 gain phase 6db/oct figure 9a. type 1 amplifier schematic diagram figure 9b. type 1 amplifier transfer function figure 10 shows an improved type 2 circuit that uses an additional pole-zero pair to temporarily remove 90 of phase shift. this allows the loop to remain stable with 90 more phase shift in the lc section, provided the loop reaches 0db gain near the center of the phase bump. out in r1 c2 c1 r2 r b 1873 f10a v ref + gain (db) phase (deg) 1873 f10b 00 ?0 180 270 phase gain ?db/oct 6db/oct figure 10a. type 2 amplifier schematic diagram figure 10b. type 2 amplifier transfer function applicatio s i for atio wu uu
22 LTC1873 modulator gain and phase can be measured directly from a breadboard, or can be simulated if the appropriate parasitic values are known. measurement will give more accurate results, but simulation can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an LTC1873 and the actual mosfets, inductor, and input and output capacitors that the final design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the LTC1873, no long wires connecting components, appropriately sized ground returns, etc. wire the feedback amplifier as a simple type 1 loop, with a 10k resistor from v out to fb and a 0.1 m f feedback capacitor from comp to fb. choose the bias resistor (r b ) as required to set the desired output voltage. disconnect r b from ground and connect it to a signal generator or to the source output of a network analyzer (figure 12) to inject a test signal into the loop. measure the gain and phase from the comp pin to the output node at the positive terminal of the output capacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the comp and v out nodes dont corrupt the measurements or damage the analyzer. if breadboard measurement is not practical, a spice simulation can be used to generate approximate gain/ phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and gener- ate an ac plot of v(v out )/v(comp) in db and phase of loop should cross through 0db in the middle of the phase bump to maximize phase margin. many LTC1873 circuits using low esr tantalum or os-con output capacitors need type 3 compensation to obtain acceptable phase margin with a high bandwidth feedback loop. feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power com- ponents shown. they should give acceptable performance with similar power components, but can be way off if even one major power component is changed significantly. applications that require optimized transient response will need to recalculate the compensation values specifically for the circuit in question. the underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. out in r1 r3 c2 c1 c3 r2 r b 1873 f11a v ref + gain (db) phase (deg) 1873 f11b 00 ?0 180 270 +6db/oct 6db/oct phase gain 6db/oct figure 11a. type 3 amplifier schematic diagram figure 11b. type 3 amplifier transfer function boost2 tg sw bg fcb fault comp fb run/ss 1/2 LTC1873 v cc 10 mbr0530t c in 5v qt 1 f v out to analyzer v comp to analyzer ac source from analyzer l ext qb 10 f 0.1 f r b pv cc sgnd pgnd + + 10k nc c out 1873 f12 + figure 12. modulator gain/phase measurement set-up applicatio s i for atio wu uu
23 LTC1873 now calculate the remaining values: (k is a constant used in the calculations) ? = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) type 2 loop: k tan boost c gkr cck r k c r vr vv b ref out ref =+ ? ? ? ? = p| = () = p| = () 2 45 2 1 21 12 1 2 21 1 2 type 3 loop: k tan boost c gr cck r k c r r k c kr r vr vv b ref out ref =+ ? ? ? ? = p| = () = p| = () = p| = () 2 4 45 2 1 21 12 1 2 21 3 1 1 3 1 23 1 v(out) in degrees. refer to your spice manual for details of how to generate this plot. *1873 modulator gain/phase * ? 1999 linear technology *this file written to run with pspice 8.0 *may require modifications for other spice simulators *mosfets rfet mod sw 0.02 ;mosfet rdson *inductor lext sw out1 1u ;inductor value rl out1 out 0.005 ;inductor series r *output cap cout out out2 1000u ;capacitor value resr out2 0 0.01 ;capacitor esr *1873 internals emod mod 0 laplace {v(comp)} = + {5*exp(Cs*909eC9)} ;5 -> 3.3 for 3.3 vcc *emod mod 0 comp 0 5 ;use if above lines fail vstim comp 0 0 ac 1 ;ac stimulus .ac dec 100 1k 1meg .probe .end with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the curves look something like figure 8. choose the crossover frequency in the rising or flat parts of the phase curve, beyond the external lc poles. frequencies between 10khz and 50khz usually work well. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback amplifier gain will be C gain to make the loop gain 0db at this frequency. now calculate the needed phase boost, assum- ing 60 as a target phase margin: boost = C (phase + 30 ) if the required boost is less than 60 , a type 2 loop can be used successfully, saving two external components. boost values greater than 60 usually require type 3 loops for satisfactory performance. finally, choose a convenient resistor value for r1 (10k is usually a good value). note that channel 1 includes r1 and r b internally as part of the vid dac circuitry. r1 is fixed at 20k and r b varies depending on the vid code selected. applicatio s i for atio wu uu
24 LTC1873 accuracy trade-offs the v ds sensing scheme used in the LTC1873 is not particularly accurate, primarily due to uncertainty in the r ds(on) from mosfet to mosfet. a second error term arises from the ringing present at the sw pin, which causes the v ds to look larger than (i load )(r ds(on) ) at the beginning of qbs on-time. these inaccuracies do not prevent the LTC1873 current limit circuit from protecting itself and the load from damaging overcurrent conditions, but they do prevent the user from setting the current limit to a tight tolerance if more than one copy of the circuit is being built. the 50% factor in the current setting equation above reflects the margin necessary to ensure that the circuit will stay out of current limit at the maximum normal load, even with a hot mosfet that is running quite a bit higher than its r ds(on) spec. fcb operation/secondary windings the fcb pin can be used in conjunction with a secondary winding on one side of the LTC1873 to generate a third regulated voltage output. this output can be directly regulated at the fcb pin. in theory, a fourth output could be added, either unregulated or with additional external circuitry at the fcb pin. the extra auxiliary output is taken from a second winding on the core of the inductor on one channel, converting it into a transformer (figure 13). the auxiliary output voltage is set by the main output voltage and the turns ratio of the extra winding to the primary winding. load regulation at the auxiliary output will be relatively good as long as the main output is running in continuous mode. as the load on the main channel drops and the LTC1873 switches to discontinuous or burst mode operation, the auxiliary output will not be able to maintain regulation, especially if the load at the auxiliary output remains heavy. to avoid this, the auxiliary output voltage is divided down with a conventional feedback resistor string with the divided auxiliary output voltage fed back to the fcb pin (figure 13). the fcb pin threshold is trimmed to 800mv current limit programming programming the current limit on the LTC1873 is straight- forward. the i max pin sets the current limit by setting the maximum allowable voltage drop across qb (the bottom mosfet) before the current limit circuit engages. the voltage across qb is set by its on-resistance and the current flowing in the inductor, which is the same as the output current. the LTC1873 current limit circuit inverts the voltage at i max before comparing it with the negative voltage across qb, allowing the current limit to be set with a positive voltage. to set the current limit, calculate the expected voltage drop across qb at the maximum desired current: vir mv prog ilim ds on = () () + () 100 i lim should be chosen to be quite a bit higher than the expected operating current, to allow for mosfet r ds(on) changes with temperature. setting i lim to 150% of the maximum normal operating current is usually safe and will adequately protect the power components if they are chosen properly. the 100mv term is an approximate factor that corrects for errors caused by ringing on the switch node (illustrated in figure 6). this factor will change depending on the layout and the components used, but 100mv is usually a good starting point. v drop is then programmed at the i max pin using the internal 10 m a pull-up and an external resistor: r ilim = v prog /10 m a the resulting value of r ilim should be checked in an actual circuit to ensure that the i lim circuit kicks in as expected. mosfet r ds(on) specs are like horsepower ratings in automobiles, and should be taken with a grain of salt. circuits that use very low values for r imax (< 20k) should be checked carefully, since small changes in r imax can cause large i lim changes when the 100mv correction factor makes up a large percentage of the total v prog value. if v prog is set too low, the LTC1873 may fail to start up. applicatio s i for atio wu uu
25 LTC1873 with 20mv of hysteresis, allowing fairly precise control of the auxiliary voltage. if the LTC1873 is in discontinuous or burst mode operation and the auxiliary output voltage drops, the fcb pin will trip and the LTC1873 will resume continuous operation regardless of the load on the main output. the fcb pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may be loaded without regard to the primary load. note that if the LTC1873 is already running in continuous mode and the auxiliary output drops due to excessive loading, no additional action can be taken by the LTC1873 to regulate the auxiliary output. later removed, the LTC1873 will latch off again unless the latch is reset by cycling the power or run/ss pins. optimizing performance maximizing high load current efficiency efficiency at high load currents (when the LTC1873 is operating in continuous mode) is primarily controlled by the resistance of the components in the power path (qt, qb, l ext ) and power lost in the gate drive circuits due to mosfet gate charge. maximizing efficiency in this region of operation is as simple as minimizing these terms. the behavior of the load over time affects the efficiency strategy. parasitic resistances in the mosfets and the inductor set the maximum output current the circuit can supply without burning up. a typical efficiency curve (figure 14) shows that peak efficiency occurs near 30% of this maximum current. if the load current will vary around the efficiency peak and will spend relatively little time at the maximum load, choosing components so that the average load is at the efficiency peak is a good idea. this puts the maximum load well beyond the efficiency peak, but usually gives the greatest system efficiency over time, which translates to the longest run time in a battery- powered system. if the load is expected to be relatively constant at the maximum level, the components should be chosen so that this load lands at the peak efficiency point, well below the maximum possible output of the converter. figure 14. typical LTC1873 efficiency curves + tg 1/2 LTC1873 bg fcb c out r fcb1 + c out(aux) v out(aux) 1873 f13 + c in qt qb v out v in r fcb2 figure 13. regulating an auxiliary output with the fcb pin fault flag the fault pin is an open-drain output that indicates if one or both of the outputs has exceeded 15% of its pro- grammed output voltage. fault includes an internal 10 m a pull-up to v cc and does not require an external pull-up to interface to standard logic. fault pulls low in normal operation, and releases when a overvoltage fault is detected. when an overvoltage fault occurs, an internal latch sets and fault goes high, disabling the LTC1873 until the latch is cleared by recycling the power or pulling both run/ss pins low simultaneously. alternately, the fault pin can be pulled back low externally with an open- collector/open-drain device or an n-channel mosfet or npn, which will allow the LTC1873 to resume normal operation, but will not reset the latch. if the pull-down is load current (a) 0 70 efficiency (%) 80 90 100 510 1873 g01 15 v in = 5v v out = 3.3v v out = 2.5v v out = 1.6v applicatio s i for atio wu uu
26 LTC1873 pin, which encompasses both reference accuracy and any op amp offset. this accounts for 1% error at the output with a 5v input supply. the feedback voltage line regula- tion spec adds an additional 0.05%/v term that accounts for change in reference output with change in input supply voltage. with a 5v supply, the errors contributed by the LTC1873 itself typically add up to less than 1% dc error at the output. at side 2, the output voltage setting resistors (r1 and r b in figure 3) are the other major contributor to dc error. at a typical 1.xv output voltage, the resistors are of roughly the same value, which tends to halve their error terms, improving accuracy. still, using 1% resistors for r1 and r b will add 1% to the total output error budget, equal to that of all errors due to the ltc1 87 3 combined. using 0.1% resistors in just those two positions can nearly halve the dc output error for very little additional cost. side 1 uses the internal vid network to set the output voltage, and is specified to be within 1.5% of the values shown in table 1. load regulation load regulation is affected by feedback voltage, feedback amplifier gain and external ground drops in the feedback path. feedback voltage is covered above and is within 1% over temperature. a full-range load step might require a 10% duty cycle change to keep the output constant, requiring the comp pin to move about 100mv. with amplifier gain at 85db, this adds up to only a 10 m v shift at fb, negligible compared to the reference accuracy terms. external ground drops arent so negligible. the LTC1873 can sense the positive end of the output voltage by attaching the feedback resistor directly at the load, but it cannot do the same with the ground lead. just 0.001 w of resistance in the ground lead at 10a load will cause a 10mv error in the output voltageas much as all the other dc errors put together. proper layout becomes essential to achieving optimum load regulation from the LTC1873. see the layout/troubleshooting section for more infor- mation. a properly laid out LTC1873 circuit should move less than a millivolt at the output from zero to full load. maximizing low load current efficiency low load current efficiency depends strongly on proper operation in discontinuous and burst mode operations. in an ideally optimized system, discontinuous mode reduces conduction losses but not switching losses, since each power mosfet still switches on and off once per cycle. in a typical system, there is additional loss in discontinuous mode due to a small amount of residual current left in the inductor when qb turns off. this current gets dissipated across the body diode of either qt or qb. some LTC1873 systems lose as much to body diode conduction as they save in mosfet conduction. the real efficiency benefit of discontinuous mode happens when burst mode operation is invoked. at typical power levels, when burst mode operation is activated, gate drive is the dominant loss term. burst mode operation turns off all output switching for several clock cycles in a row, significantly cutting gate drive losses. as the load current in burst mode operation falls toward zero, the current drawn by the circuit falls to the LTC1873s background quiescent levelabout 3ma per channel. to maximize low load efficiency, make sure the LTC1873 is allowed to enter discontinuous and burst mode opera- tion as cleanly as possible. fcb must be above its 0.8v threshold. minimize ringing at the sw node so that the discontinuous comparator leaves as little residual current in the inductor as possible when qb turns off. it helps to connect the sw pin of the LTC1873 as close to the drain of qb as possible. an rc snubber network can also be added from sw to pgnd. regulation over component tolerance/ temperature dc regulation accuracy the LTC1873 initial dc output accuracy depends mainly on internal reference accuracy, op amp offset and external resistor accuracy (side 2 only). two LTC1873 specs come into play: feedback voltage and feedback voltage line regulation. the feedback voltage spec is 800mv 8mv over the full temperature range, and is specified at the fb applicatio s i for atio wu uu
27 LTC1873 transient response transient response is the other half of the regulation equation. the LTC1873 can keep the dc output voltage constant to within 1% when averaged over hundreds of cycles. over just a few cycles, however, the external components conspire to limit the speed that the output can move. consider our typical 5v to 1.5v circuit, subjected to a 1a to 5a load transient. initially, the loop is in regulation and the dc current in the output capacitor is zero. suddenly, an extra 4a start flowing out of the output capacitor while the inductor is still supplying only 1a. this sudden change will generate a (4a)(c esr )voltage step at the output; with a typical 0.015 w output capacitor esr, this is a 60mv step at the output, or 4% (for a 1.5v output voltage). very quickly, the feedback loop will realize that something has changed and will move at the bandwidth allowed by the external compensation network towards a new duty cycle. if the bandwidth is set to 50khz, the comp pin will get to 60% of the way to 90% duty cycle in 3 m s. now the inductor is seeing 3.5v across itself for a large portion of the cycle, and its current will increase from 1a at a rate set by di/dt = v/l. if the inductor value is 0.5 m h, the di/dt will be 3.5v/0.5 m h or 7a/ m s. sometime in the next few micro- seconds after the switch cycle begins, the inductor current will have risen to the 5a level of the load current and the output capacitor will stop losing charge. note that the output voltage will stop dropping before the inductor current reaches this new output current level. recall that any practical output capacitor looks like a pure capacitance in series with some amount of esr. when a load transient hits, virtually all of the initial voltage drop at the output is due to ir drop across the esr. the output capacitance begins to discharge at the same time and continues until the inductor current rises to match the new output current level. the output voltage, however, will turn around and start heading the right way before this happens. the next time the top mosfet turns on, the inductor current will begin increasing linearly. this increasing current flows almost entirely into the capacitor, going through the esr as it does so (figure 15). positive di/dt in the inductor causes positive dv/dt in the esr, regardless of what the pure capacitance is doing. the output voltage will turn around when the positive dv/dt across the esr exceeds the negative dv/dt across the pure capacitance. if the expected load step ( d i) is known, an optimum inductor value can be chosen: lv v c esr i in out () d making l smaller than this optimum value yields little or no improvement in transient response. as the output voltage recovers, the inductor current will briefly rise above the level of the output current to replenish the charge lost from the output capacitor. with a properly compensated loop, the entire recovery time will be inside of 10 m s. most loads care only about the maximum deviation from ideal, which occurs somewhere in the first two cycles after the load step hits. during this time, the output capacitor does all the work until the inductor and control loop regain control. the initial drop (or rise if the load steps down) is entirely controlled by the esr of the capacitor and amounts to most of the total voltage drop. to minimize this drop, reduce the esr as much as possible by choosing low esr capacitors and/or paralleling multiple capacitors at the output. the capacitance value accounts for the rest of the voltage drop until the inductor current rises. with most output capacitors, several devices paralleled to get the esr down will have so much capacitance that this drop term is negligible. ceramic capacitors are an exception; a small ceramic capacitor can have suitably low esr with relatively small values of capacitance, making this second drop term significant. optimizing loop compensation loop compensation has a fundamental impact on tran- sient recovery time, the time it takes the LTC1873 to recover after the output voltage has dropped due to output capacitor esr. optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability. the feedback component applicatio s i for atio wu uu
28 LTC1873 figure 15a. capacitor parasitics affecting transient recovery figure 15b. transient recovery curves + i l v out i out 1873 f15a v esr c out v cap v sw l + v cap v out transient hits v out turns around i l > i out time v esr i out i l v out v esr i out i l v cap v out(nominal) 1873 f15b selection section describes in detail how to design an optimized feedback loop, appropriate for most LTC1873 systems. voltage positioning if the load transients consist primarily of load steps from near zero load to full load and back, the transient response can be traded off against dc regulation performance by using a technique known as voltage positioning. the goal is to intentionally compromise the dc regulation loop such that the output rides near the maximum allowable value (often +5%) with no load and near the minimum allowable value at maximum load. with the load at zero, any transient that comes along will be a current increase which will cause the output voltage to fall. since the output voltage is initially at a high value, it can fall further before it goes out of spec. similarly, at full load, the output current can only decrease, causing a positive shift in the output voltage; the initial low value allows it to rise further before the spec is exceeded. the primary benefit of voltage positioning is it increases the allowable esr of the output capacitors, saving cost. an additional bonus is that at maximum load, the output voltage is near the minimum allowable, decreasing the power dissipated in the load. applicatio s i for atio wu uu
29 LTC1873 implementing voltage positioning is as simple as creating an intentional resistance in the output path to generate the required voltage drop. this resistance can be a low value resistor, a length of pcb trace, or even the parasitic resistance of the inductor if an appropriate filter is used. if the LTC1873 senses the output voltage upstream from the resistance (figure 16c), the output voltage will move with load as i ? r vp , where i is the load current and r vp is the value of the voltage positioning resistor. if the feedback network is then reset to regulate near the upper edge of the specified tolerance, the output voltage will ride high when i load is low and will ride low when i load is high. compared to a traditional regulator (figure 16a), a voltage position- ing regulator can theoretically stand as much as twice the esr drop across the output capacitor while maintaining output voltage regulation. this means smaller, cheaper output capacitors can be used while keeping the output voltage within acceptable limits. measurement techniques measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gener- ating a suitable transient to use to test the circuit. output measurements should be taken with a scope probe directly across the output capacitor. proper high fre- quency probing techniques should be used. in particular, dont use the 6" ground lead that comes with the probe! use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path doesnt cause a bigger spike than the transient signal being measured. conveniently, the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use LTC1873 fb 1873 f16a 1873 f16b v out v in +5% ?% nom max 0 v out load current maximum allowable transient figure 16a. standard regulator figure 16b. standard regulator?ransient response LTC1873 fb 1873 f16c 1873 f16d v out v in voltage positioning resistor (r vp ) +5% ?% nom max time time 0 v out load current figure 16c. voltage positioning regulator figure 16d. positioning regulator?ransient response maximum allowable transient 2 figure 16b + + applicatio s i for atio wu uu
30 LTC1873 the actual load for the test, and switch it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the LTC1873 and the transient generator must be minimized. figure 17 shows an example of a simple transient genera- tor. be sure to use a noninductive resistor as the load elementmany power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w film resistors and wire them in parallel to get the desired value. surface mount resistors are best. this gives a noninductive resistive load which can dissi- pate 2.5w continuously or 50w if pulsed with a 5% duty cycle, enough for most LTC1873 circuits. solder the mosfet and the resistor(s) as close to the output of the LTC1873 circuit as possible and set up the signal genera- tor to pulse at a 100hz rate with a 5% duty cycle. this pulses the LTC1873 with 500 m s transients 10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. figure 17. transient load generator changing the output voltage on the fly the voltage at side 1 of the LTC1873 can be changed on the fly by changing the vid code while the output is enabled, but care must be taken to avoid tripping the overvoltage fault circuit. stepping the voltage upwards abruptly is safe, but stepping down quickly by more than 15% can leave the system in a state where the output voltage is still at the old higher level, but the feedback node is set to expect a new, substantially lower voltage. if this condition persists for more than 10 m s, the overvoltage fault circuitry will fire and latch off the LTC1873. the simplest solution is to disable the fault circuit by grounding the fault pin. systems that must keep the fault circuit active should ensure that the output voltage is never programmed to step down by more than 15% in any single step. the safest strategy is to step the output down by 10% or less at a time and wait for the output to settle to the new value before taking subsequent steps. LTC1873 pulse generator 1873 f17 irfz44 or equivalent 50 0v to 10v 100hz, 5% duty cycle v out r load locate close to the output applicatio s i for atio wu uu
31 LTC1873 dimensions in inches (millimeters) unless otherwise noted. g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 13 10.07 ?10.33* (0.397 ?0.407) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio
32 LTC1873 1873f lt/tp 0200 4k ? printed in usa ? linear technology corporation 1999 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments ltc1530 high power synchronous step-down controller so-8 with current limit. no r sense required ltc1628 dual high efficiency 2-phase synchronous step-down controller constant frequency, standby 5v and 3.3v ldos, 3.5v v in 36v ltc1702 dual high efficiency 2-phase synchronous step-down controller 550khz, 25mhz gbw voltage mode, v in 7v, no r sense tm ltc1703 dual 550khz synchronous 2-phase switching regulator controller ltc1702 with mobile vid for portable systems with mobile vid ltc1706-19 vid voltage programmer adds 4-bit mobile pentium ii vid to all1.19v referenced switching regulators ltc1706-81/82 desktop vid voltage programmer for vrm 8.4/vrm 9.0 adds 5-bit desktop vid to all 0.8v referenced regulators ltc1709 2-phase, 5-bit vid synchronous step-down controller current mode, v in to 36v, i out up to 42a ltc1736 synchronous step-down controller with 5-bit vid control fault protection, powergood, 3.5v to 36v input, current mode ltc1753 5-bit programmable synchronous switching rregulator 1.3v to 3.5v programmable output using internal 5-bit dac ltc1929 2-phase, synchronous high efficiency converter current mode ensures accurate current sensing, v in up to 36v, i out up to 42a no r sense is a trademark of linear technology corporation. single output, 2-phase, 25a vid converter (v in = 5v, v out = 1.3v to 3.5v) v cc boost1 tg1 sw1 bg1 comp1 fb1 sense run/ss1 i max1 boost2 fault 47k 47k 22k 11k 120pf 220pf 220pf 0.1 f 1 f q1 q3 q2 330pf 1 1 1 10 1 1873 ta02 v out 1.3v to 3.5v 25a tg2 sw2 bg2 comp2 fb2 run/ss2 i max2 pv cc sgnd pgnd vid1:0 vid4:2 vid1:0 fcb mbr 330t l2 1 h mbr 330t mbr0530t LTC1873 mbr 0530t q4 q6 q5 120pf + 10k 10k 0.003 0.5w 0.003 0.5w v in 5v 11k 20k 10k 10k 330pf 2 7 5 4 6 0.1 f 3 1 f 0.1 f 10 f + lt 1218 + 470 f* + 470 f* 470 f* 2 *kemet t510x477m006as q1 to q6: fairchild fds6670a l1, l2: murata lqt12535c1r5n12 + 470 f* + l1 1 h fault vid4:2 typical applicatio u

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